Hardware Hacking

CY2CC810 Description
1:10 Clock Fanout Buffer
CY2CC810 Vendor
Cypress
CY2CC810 Categories
Clock Fanout Buffers

CY2CC810 Features
Low-voltage operation
VDD range from 2.5V to 3.3V
1:10 fanout
Over voltage tolerant input hot swappable
Drives either a 50-Ohm or 75-Ohm transmission line
Low-input capacitance
Low-output skew
Low-propagation delay
Typical (tpd < 4 ns)
High-speed operation > 500 MHz
Industrial versions available
Available packages include: SOIC, SSOP

CY2CC810 Datasheet and Application Notes
CY2CC810 Datasheet

Parameter Value
Features 1:10 AVCMOS Clk Fanout Buffer
Functions 1:10 Fanout
Outputs 10
Voltage (V) 2.5/3.3
Operating Range Commercial/Industrial
Package 20 SSOP / 20 SOIC
Status *Full Production
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CY29947 Description
2.5V or 3.3V operation
CY29947 Vendor
Cypress
CY29947 Categories
Clock Fanout Buffers

CY29947 Features
2.5V or 3.3V operation
200-MHz clock support
LVCMOS-/LVTTL-compatible inputs
9 clock outputs: drive up to 18 clock lines
Synchronous Output Enable
Output three-state control
250 ps max. output-to-output skew
Pin compatible with MPC947, MPC9447
Available in Industrial and Commercial temp. range
32-pin TQFP package

CY29947 Datasheet and Application Notes
CY29947 Datasheet

Products related to CY29947
CY29947AC CY29947AI

CY29946 Description
2.5V or 3.3V, 200-MHz, 1:10 Clock Distribution Buffer
CY29946 Vendor
Cypress
CY29946 Categories
Clock Fanout Buffers

CY29946 Features
2.5V or 3.3V operation
200-MHz clock support
Two LVCMOS-/LVTTL-compatible inputs
Ten clock outputs: drive up to 20 clock lines
1× or 1/2× configurable outputs
Output three-state control
250-ps max. output-to-output skew
Pin-compatible with MPC946, MPC9446
Available in commercial and industrial temperature range
32-pin TQFP package

CY29946 Description
The CY29946 is a low-voltage 200-MHz clock distribution buffer with the capability to select one of two LVCMOS/LVTTL compatible input clocks. These clock sources can be used to provide for test clocks as well as the primary system clocks. All other control inputs are LVCMOS/LVTTL compatible. The 10 outputs are LVCMOS or LVTTL compatible and can drive 50. series or parallel terminated transmission lines. For series terminated transmission lines, each output can drive one or two traces giving the device an effective fanout of 1:20. The CY29946 is capable of generating 1× and 1/2× signals from a 1× source. These signals are generated and retimed internally to ensure minimal skew between the 1× and 1/2× signals. SEL(A:C) inputs allow flexibility in selecting the ratio of 1× to1/2× outputs.

CY29946 Datasheet and Application Notes
CY29946 Datasheet

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CY29943 Description
200-MHz clock support
CY29943 Vendor
Cypress
CY29943 Categories
Clock Fanout Buffers

CY29943 Features
200-MHz clock support
2.5V or 3.3V operation
LVPECL clock input
LVCMOS-/LVTTL-compatible inputs
18 clock outputs: drive up to 36 clock lines
200 ps max. output-to-output skew
Output Enable control
Pin compatible with MPC942P
Available in Industrial and Commercial
32-pin LQFP package

CY29943 Datasheet and Application Notes
CY29943 Datasheet

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CY29973 Description
3.3V 125-MHz Multi-Output Zero Delay Buffer
CY29973 Vendor
Cypress
CY29973 Categories
Clock Fanout Buffers

CY29973 Features
Output Frequency up to 125 MHz
12 Clock Outputs: Frequency Configurable
350-ps max. Output to Output Skew
Configurable Output Disable
Two Reference Clock Inputs for Dynamic Toggling
Oscillator or PECL Reference Input
Spread Spectrum Compatible
Glitch-free Output Clocks Transitioning
3.3V Power Supply
Pin-compatible with MPC973
Industrial Temp. Rang: –40°C to +85°C
52-Pin TQFP Package

CY29973 Description
The CY29973 has an integrated PLL that provides low-skew and low-jitter clock outputs for high-performance microprocessors. Three independent banks of four outputs as well as an independent PLL feedback output, FB_OUT, provide exceptional flexibility for possible output configurations. The PLL is ensured stable operation given that the VCO is configured to run between 200 MHz to 480 MHz. This allows a wide range of output frequencies up to125 MHz.

The phase detector compares the input reference clock to the external feedback input. For normal operation, the external feedback input, FB_IN, is connected to the feedback output, FB_OUT. The internal VCO is running at multiples of the input reference clock set by FB_SEL(0:2) and VCO_SEL select inputs, refer to Table 1. The VCO frequency is then divided down to provide the required output frequencies. These dividers are set by SELA(0,1), SELB(0,1), SELC(0,1) select inputs, see Table 2 below. For situations were the VCO needs to run at relatively low frequencies and hence might not be stable, assert VCO_SEL LOW to divide the VCO frequency by 2. This will maintain the desired output relationships, but will provide an enhanced PLL lock range.

The CY29973 is also capable of providing inverted output clocks. When INV_CLK is asserted high, QC2 and QC3 output clocks are inverted. These clocks could be used as feedback outputs to the CY29973 or a second PLL device to generate early or late clocks for a specific design. This inversion does not affect the output to output skew.

CY29973 Datasheet and Application Notes
CY29973 Datasheet

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