Hardware Hacking

CY29940 Description
200-MHz clock support
CY29940 Vendor
Cypress
CY29940 Categories
Clock Fanout Buffers

CY29940 Features
200-MHz clock support
LVPECL or LVCMOS/LVTTL clock input
LVCMOS/LVTTL compatible inputs
18 clock outputs: drive up to 36 clock lines
150 ps max. output-to-output skew
Dual or single supply operation:

3.3V core and 3.3V outputs
3.3V core and 2.5V outputs
2.5V core and 2.5V outputs
Pin compatible with MPC940L, MPC9109
Available in Commercial and Industrial temperature
32-pin LQFP package

CY29940 Datasheet and Application Notes
CY29940 Datasheet

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CY2CC1810 Description
Low-voltage operation
CY2CC1810 Vendor
Cypress
CY2CC1810 Categories
Clock Fanout Buffers

CY2CC1810 Features
Low-voltage operation
VDD range from 2.5 to 3.3V
1:10 fanout
Drives either a 50-ohm or 75-ohm transmission line
Over voltage tolerant input hot swappable
Low input capacitance
Low output skew
Low propagation delay
Typical (tpd < 4 ns)
High-speed operation > 200 MHz
LVTTL-/LVCMOS-compatible input
Output disable to three-state
Industrial versions available
Packages available include: SOIC/SSOP

CY2CC1810 Datasheet and Application Notes
CY2CC1810 Datasheet

Parameter Value
Features 1:10 AVCMOS Clk Fanout Buffer w/tri state outputs
Functions 1:10 Fanout
Outputs 10
Voltage (V) 2.5/3.3
Operating Range Commercial/Industrial
Package 24 SSOP / 24 SOIC
Status *Full Production
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CY29774 Description
Clocks and Buffers : Clock Distribution
CY29774 Vendor
Cypress
CY29774 Categories
Clock Fanout Buffers

CY29774 Features
Output frequency range: 8.3 MHz to 125 MHz
Input frequency range: 4.2 MHz to 62.5 MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
14 Clock outputs: Drive up to 28 clock lines
1 Feedback clock output
2 LVCMOS reference clock inputs
150 ps max output-output skew
PLL bypass mode
Spread Awareâ„¢
Output enable/disable
Pin compatible with MPC9774
Industrial temperature range: –40°C to +85°C
52-Pin 1.0-mm TQFP package

CY29774 Datasheet and Application Notes
CY29774 Datasheet

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CY29972 Description
3.3V, 125-MHz Multi-Output Zero Delay Buffer
CY29972 Vendor
Cypress
CY29972 Categories
Clock Fanout Buffers

CY29972 Features
Output frequency up to 125 MHz
12 Clock outputs: frequency configurable
350 ps max. output-to-output skew
Configurable output disable
Two reference clock inputs for dynamic toggling
Oscillator or crystal reference input
Spread-spectrum-compatible
Glitch-free output clocks transitioning
3.3V power supply
Pin-compatible with MPC972
Industrial temperature range: –40°C to +85°C
52-pin TQFP package

CY29972 Datasheet and Application Notes
CY29972 Datasheet

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CY29773 Description
2.5V or 3.3V, 200-MHz, 12-Output Zero Delay Buffer
CY29773 Vendor
Cypress
CY29773 Categories
Clock Fanout Buffers

CY29773 Features
Output frequency range: 8.33 MHz to 200 MHz
Input frequency range: 6.25 MHz to 125 MHz
2.5V or 3.3V operation
Split 2.5V/3.3V outputs
±2% max Output duty cycle variation
12 Clock outputs: drive up to 24 clock lines
One feedback output
Three reference clock inputs: LVPECL or LVCMOS
300-ps max output-output skew
Phase-locked loop (PLL) bypass mode
Spread AwareTM
Output enable/disable
Pin-compatible with MPC9773 and MPC973
Industrial temperature range: –40°C to +85°C
52-pin 1.0-mm TQFP package

CY29773 Description
The CY29773 is a low-voltage high-performance 200-MHz PLL-based zero delay buffer designed for high speed clock distribution applications.

The CY29773 features one LVPECL and two LVCMOS reference clock inputs and provides 12 outputs partitioned in three banks of four outputs each. Each bank divides the VCO output per SEL(A:C) settings (see Table 2. Function Table (Configuration Controls)). These dividers allow output-to-input ratios of 8:1, 6:1, 5:1, 4:1, 3:1, 8:3, 5:2, 2:1, 5:3, 3:2, 4:3, 5:4, 1:1, and 5:6. Each LVCMOS-compatible output can drive 50W series- or parallel-terminated transmission lines. For series-terminated transmission lines, each output can drive one or two traces, giving the device an effective fanout of 1:24.

The PLL is ensured stable, given that the VCO is configured to run between 200 MHz to 500 MHz. This allows a wide range of output frequencies, from 8 MHz to 200 MHz. For normal operation, the external feedback input FB_IN is connected to the feedback output FB_OUT. The internal VCO is running at multiples of the input reference clock set by the feedback divider (see Table 1. Frequency Table).

When PLL_EN is LOW, PLL is bypassed and the reference clock directly feeds the output dividers. This mode is fully static and the minimum input clock frequency specification does not apply.

CY29773 Datasheet and Application Notes
CY29773 Datasheet

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