CY2DL818
CY2DL818 Description
Low voltage operation
CY2DL818 Vendor
Cypress
CY2DL818 Categories
Clock Fanout Buffers
CY2DL818 Features
Low voltage operation
VDD = 3.3V
1:8 fanout
Single-input-configurable for LVDS, LVPECL, or LVTTL
Eight pair of LVDS outputs
Drives either a 50-ohm or 100-ohm load (selectable)
Low input capacitance
Low output skew
Low propagation delay
Typical (tpd < 4 ns)
Packages available include: TSSOP
Does not exceed Bellcore 802.3 standards
Operation at => 350 MHz – 700 Mbps
CY2DL818 Description
This Cypress series of network circuits is produced using advanced 0.35-micron CMOS technology, achieving the industry’s fastest logic.
The Cypress CY2DL818 fanout buffer features a single LVDS or a single-ended LVTTL-compatible input and eight LVDS output pairs.
Designed for data communications clock management applications, the large fanout from a single input reduces loading on the input clock. The Cypress CY2DL818 is ideal for both level translations from single-ended to LVDS and/or for the distribution of LVDS-based clock signals.
The Cypress CY2DL818 has configurable input and output functions. The input can be selectable for LVCMOS/LVTTL, LVPECL, or LVDS signals, while the output driver’s support standard and high-drive LVDS. Drive either a 50-ohm or 100-ohm line with a single part number/device.
CY2DL818 Datasheet and Application Notes
CY2DL818 Datasheet
Parameter Value
Features 1:8 Differential to LVDS Clk Fanout Buffer
Functions 1:8 Fanout
Outputs 8
Voltage (V) 3.3
Operating Range Commercial/Industrial
Package 38 TSSOP
Status *Full Production
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