Hardware Hacking

CY2DP3120 Description
1:20 Differential Clock/Data Fanout Buffer
CY2DP3120 Vendor
Cypress
CY2DP3120 Categories
Clock Fanout Buffers

CY2DP3120 Features
Twenty ECL/PECL differential outputs
One ECL/PECL compatible differential or single-ended clock inputs
One HSTL compatible differential or single-ended clock inputs
Hot-swappable/-insertable
50 ps output-to-output skew
150 ps device-to-device skew
500 ps propagation delay (typical)
1.4 ps RMS period jitter (max.)
1.5 GHz Operation (2.7 GHz max. toggle frequency)
PECL mode supply range: VCC = 2.5V± 5% to 3.3V±5% with VEE = 0V
ECL mode supply range: VE E = –2.5V± 5% to –3.3V±5% with VCC = 0V
Industrial temperature range: –40°C to 85°C
52-pin 1.4-mm TQFP package
Temperature compensation like 100K ECL
Pin compatible with MC100ES6221

CY2DP3120 Description
The CY2DP3120 is a low-skew, low propagation delay 1-to-20 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies of up to 1.5 GHz.

The device features two differential input paths that are multiplexed internally. This mux is controlled by the CLK_SEL pin. The CY2DP3120 may function not only as a differential clock buffer but also as a signal-level translator and fanout on ECL/PECL signal to twenty ECL/PECL differential loads. An external bias pin, VBB, is provided for this purpose. In such an application, the VBB pin should be connected to either one of the CLKA# or CLKB# inputs and bypassed to ground via a 0.01-µF capacitor. Traditionally, in ECL, it is used to provide the reference level to a receiving single-ended input that might have a different self-bias point.

Since the CY2DP3120 introduces negligible jitter to the timing budget, it is the ideal choice for distributing high frequency, high precision clocks across back-planes and boards in communication systems. Furthermore, advanced circuit design schemes, such as internal temperature compensation, ensure that the CY2DP3120 delivers consistent performance over various platforms.

CY2DP3120 Datasheet and Application Notes
CY2DP3120 Datasheet

Parameter Value
Features 2:10 PECL/ECL/HSTL Fanout Buffer
Functions 1:20 Fanout
Outputs 20
Voltage (V) 2.5/3.3
Operating Range Industrial
Package 52 TQFP
Status *Sample
Products related to CY2DP3120
CY2DP3120AI

CY2DP814 Description
1:4 Clock Fanout Buffer
CY2DP814 Vendor
Cypress
CY2DP814 Categories
Clock Fanout Buffers

CY2DP814 Features
Low voltage operation
VDD = 3.3V
1:4 fanout
Single-input configurable for LVDS, LVPECL, or LVTTL
Four differential pairs of LVPECL outputs
Drives 50-ohm load
Low input capacitance
Low output skew
Low propagation delay
Typical (tpd < 4 ns)
Industrial versions available
Available packages include TSSOP, SOIC

CY2DP814 Datasheet and Application Notes
CY2DP814 Datasheet

Parameter Value
Features 1:4 Differential to LVPECL Clk Fanout Buffer
Functions 1:4 Fanout
Outputs 4
Voltage (V) 3.3
Operating Range Commercial/Industrial
Package 16 SOIC / 16 TSSOP
Status *Full Production
Products related to CY2DP814
CY2DP814ZI CY2DP814ZC CY2DP814SI CY2DP814SC

CY2DP3110 Description
1 of 2:10 Differential Clock/Data Fanout Buffer
CY2DP3110 Vendor
Cypress
CY2DP3110 Categories
Clock Fanout Buffers

CY2DP3110 Features
Ten ECL/PECL differential outputs
One ECL/PECL differential or single-ended inputs (CLKA)
One HSTL differential or single-ended inputs (CLKB)
Hot-swappable/-insertable
50 ps output-to-output skew
150 ps device-to-device skew
400 ps propagation delay (typical)
1.2 ps RMS period jitter (max.)
1.5 GHz Operation (2.7 GHz maximum toggle frequency)
PECL and HSTL mode supply range: VCC = 2.5V± 5% to 3.3V±5% with VEE = 0V
ECL mode supply range: VE E = –2.5V± 5% to –3.3V±5% with VCC = 0V
Industrial temperature range: –40°C to 85°C
32-pin TQFP package
Temperature compensation like 100K ECL
Pin-compatible with MC100ES6111

CY2DP3110 Description
The CY2DP3110 is a low-skew, low propagation delay 2-to-10 differential fanout buffer targeted to meet the requirements of high-performance clock and data distribution applications. The device is implemented on SiGe technology and has a fully differential internal architecture that is optimized to achieve low signal skews at operating frequencies of up to 1.5 GHz.

The device features two differential input paths that are multiplexed internally. This mux is controlled by the CLK_SEL pin. The CY2DP3110 may function not only as a differential clock buffer but also as a signal-level translator and fanout on HSTL single-ended signal to 10 ECL/PECL differential loads. An external bias pin, VBB, is provided for this purpose. In such an application, the VBB pin should be connected to either one of the CLKA# or CLKB# inputs and bypassed to ground via a 0.01-µF capacitor. Traditionally, in ECL, it is used to provide the reference level to a receiving single-ended input that might have a different self-bias point.

Since the CY2DP3110 introduces negligible jitter to the timing budget, it is the ideal choice for distributing high frequency, high precision clocks across back-planes and boards in communication systems. Furthermore, advanced circuit design schemes, such as internal temperature compensation, ensure that the CY2DP3110 delivers consistent performance over various platforms

CY2DP3110 Datasheet and Application Notes
CY2DP3110 Datasheet

Products related to CY2DP3110
CY2DP3110AI

CY2DL818 Description
Low voltage operation
CY2DL818 Vendor
Cypress
CY2DL818 Categories
Clock Fanout Buffers

CY2DL818 Features
Low voltage operation
VDD = 3.3V
1:8 fanout
Single-input-configurable for LVDS, LVPECL, or LVTTL
Eight pair of LVDS outputs
Drives either a 50-ohm or 100-ohm load (selectable)
Low input capacitance
Low output skew
Low propagation delay
Typical (tpd < 4 ns)
Packages available include: TSSOP
Does not exceed Bellcore 802.3 standards
Operation at => 350 MHz – 700 Mbps

CY2DL818 Description

This Cypress series of network circuits is produced using advanced 0.35-micron CMOS technology, achieving the industry’s fastest logic.

The Cypress CY2DL818 fanout buffer features a single LVDS or a single-ended LVTTL-compatible input and eight LVDS output pairs.

Designed for data communications clock management applications, the large fanout from a single input reduces loading on the input clock. The Cypress CY2DL818 is ideal for both level translations from single-ended to LVDS and/or for the distribution of LVDS-based clock signals.

The Cypress CY2DL818 has configurable input and output functions. The input can be selectable for LVCMOS/LVTTL, LVPECL, or LVDS signals, while the output driver’s support standard and high-drive LVDS. Drive either a 50-ohm or 100-ohm line with a single part number/device.

CY2DL818 Datasheet and Application Notes
CY2DL818 Datasheet

Parameter Value
Features 1:8 Differential to LVDS Clk Fanout Buffer
Functions 1:8 Fanout
Outputs 8
Voltage (V) 3.3
Operating Range Commercial/Industrial
Package 38 TSSOP
Status *Full Production
Products related to CY2DL818
CY2DL818ZC CY2DL818ZI

CY2DL814 Description
Low-voltage operation
CY2DL814 Vendor
Cypress
CY2DL814 Categories
Clock Fanout Buffers

CY2DL814 Features
Low-voltage operation
VDD = 3.3V
1:4 Fanout
Single-input configurable for
LVDS, LVPECL, or LVTTL
Four differential pairs of LVDS outputs
Drives 50- or 100-ohm load (selectable)
Low input capacitance
Low output skew
Does not exceed Bellcore 802.3 standards
Operation at » 350 MHz – 700 Mbps
Low propagation delay Typical (tpd < 4 ns)
Industrial versions available
Packages available include TSSOP/SOIC

CY2DL814 Datasheet and Application Notes
CY2DL814 Datasheet

Parameter Value
Features 1:4 Differential to LVDS Clk Fanout Buffer
Functions 1:4 Fanout
Outputs 4
Voltage (V) 3.3
Operating Range Commercial/Industrial
Package 16 SOIC / 16 TSSOP
Status *Full Production
Products related to CY2DL814
CY2DL814SI CY2DL814ZI CY2DL814ZC CY2DL814SC